This invention relates to a voltage comparator, and more particularly to a voltage comparator having a plurality of capacitively cascade-connected inverting amplifiers.
An analog-to-digital converter (hereinafter referred to as "an A/D converter") such as a successive--approximation converter already known in the art comprises a comparator for comparing an unknown analog voltage Va supplied from a sample-and-hold circuit with a corresponding output voltage Vo from a digital-to-analog (D/A) converter which approximates the unknown analog voltage Va from the sample-and-hold circuit. This voltage comparator produces an output signal of a logic level 1 or 0 according to the relationship between the magnitudes of the voltage signals Va and Vo being compared. As is well known, an output signal from the comparator is conducted to a register section of the A/D converter.
FIG. 1 shows the arrangement of a prior art comparator used in a successive-approximation A/D converter including capacitively cascade--connected inverting amplifiers. The conventional comparator comprises N stages of inverting amplifiers. The respective amplifier stages are comprised of MOS inverters 1-1, 1-2,--and 1-N and coupling capacitors 2-1, 2-2,--and 2-N. The inputs of inverters 1-1, 1-2,--and 1-N are connected through source-to-drain paths of MOS transistors 3-1, 3-2,--and 3-N to the dividing point of a voltage divider formed of resistors R.sub.a and R.sub.b which may be formed by MOS transistor and connected across a power source V.sub.D. The two voltage signals Vo and Va to be compared are alternately applied to the coupling capacitor 2-1 of the first stage amplifier through source-to-drain paths of MOS transistors 4 and 5. A clock pulse .phi. is delivered to the gate electrodes of MOS transistors 3-1, 3-2, 3-N and 4, and a complementary clock pulse .phi. is supplied to the gate electrode of MOS transistor 5. In FIG. 1, the MOS transistors are of the N-channel type, and the MOS inverters are each formed, as is well known, of an N-channel driving MOS transistor and an N-channel load MOS transistor. Further, all the above-mentioned MOS transistors are of the enhancement type. The MOS transistors 3-1, 3-2, 3-N and 4 are enabled and MOS transistor 5 is disabled when the clock pulse .phi. goes high. Conversely, when the clock pulse .phi. goes low, that is, when the complementary clock pulse .phi. goes high, the MOS transistor 5 is enabled, whereas the MOS transistors 3-1, 3-2, 3-N and 4 are disabled. As a result, the voltage signals Vo and Va are alternately coupled to the first stage amplifier during the cycle period of clock pulses .phi. and .phi..
When the MOS transistors 3-1, 3-2 and 3-N are enabled, the inputs of MOS inverters are biased to an output voltage V.sub.bias from the voltage divider. Since, at this time, the MOS transistor 4 is enabled, the output voltage Vo from the D/A converter included in the successive-approximation A/D converter is applied to the first stage coupling capacitor 2-1, which in turn is charged to Vo-V.sub.bias. When the clock pulse .phi. goes high, the unknown analog voltage Va from the sample-and-hold circuit which is to be converted into a digital signal is supplied to the first stage coupling capacitor 2-1 in place of the output voltage Vo from the D/A converter. At this time, the MOS transistor 3-1 is rendered nonconducting to interrupt the discharging path for the first stage coupling capacitor 2-1. As a result, an input potential of the MOS inverter 1-1 is changed so as to maintain the voltage Vo-V.sub.bias across the capacitor 2-1. Thus, the input potential of the MOS inverter 1-1 is changed from the voltage V.sub.bias by the extent of Va-Vo. This potential change is progressively invert-amplified through the cascade-connected inverting amplifiers. The level of an output voltage from the last stage amplifier is defined by the relationship between the magnitudes of the two voltage signals Vo and Va being compared as well as by an odd or even number of inverting amplifiers used. The number of the inverting amplifiers can be reduced more, according as the inverting amplifier has a larger amplification factor. The above-mentioned prior art voltage comparator can be integrated with other circuits on a semiconductor chip.
FIG. 2 shows a typical transfer characteristic or input-output characteristic of an inverter. As seen from FIG. 2, each of the inverting amplifiers included in the comparator operates in the best mode when its operation point is set by the bias voltage V.sub.bias at the central point P of the transition region of transfer characteristic lying between the output logic levels 1 and 0. Inverters 1-1, 1-2, 1-N formed on the same semiconductor chip have substantially the same transfer characteristic. However, inverters formed on different semiconductor chips unavoidably indicate unequal transfer characteristics due to manufacturing process variations. Further, the resistance values of resistors Ra and Rb constituting the voltage divider vary from chip to chip. Since the supply voltage V.sub.D used is considered to remain unchanged for a number of semiconductor chips manufactured, the manufacturing process variations may cause the operation point of the inverter to be displaced from the optimum point. In the worst case, where, for example, the transition region of the transfer characteristic curve is inclined prominently, then the inverter is operated at the point where the bias voltage V.sub.bias causes an output voltage signal always to have a logic level of either 1 or 0. In such case, the comparator fails to be properly operated.